Backside roughness variation on incoming silicon-on-insulator (SOI) wafers (or other types of wafers) causes measurable process variations that result in negative effects on yield. In particular, less backside roughness has resulted in poor etch performance due to a decrease in wafer temperature (increased contact to chuck, which sinks heat), which leads to lower etch selectivity.
By way of example, variations in backside roughness between vendors and even wafers received from the same vendor, results in lower etch selectivity which, in turn, results in different contact resistance. Due to the backside roughness variations amongst different vendors or even different lots of the same vendor, random variations still occur which make it difficult to adjust process variations. Techniques to overcome these issues have been tried, but not with success.
For example, gas flow can be adjusted to correct the temperature, but due to variations among vendors, there still remains a concern that such adjustments cannot be made with much consistency. Physical polishing techniques add cost. In addition, polishing may still be inadequate for controlling this problem because there may be variation in roughness after the polish. Also, grinding processes can degrade the integrity of the substrate and current chucking methods involve adhering the front side of the wafer to a glass plate. This latter process may disturb the incoming clean top surface of the wafer, which is critical to front end processing.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.